UVM RAL model is Register Abstraction Layer which simplifies register verification of ASIC.
It is actually mirror image class of register module in RTL in verification environment. It is created by using uvm_reg_field , uvm_reg, uvm_reg_block . Simulation tools available which converts IP_XACT format register description to RAL model (e.g. ralgen) . Once register model is created, internal methods read/write/update can be used in any sequence.
So , Below are phases of using UVM RAL model in verification environment.
- RAL model generation and integration and mapping.
- Making adaptor /predictor or both as per requirement.
- Using UVM sequence for default read and write read register operations
- Use of RAL model in other sequences except uvm inbuilt sequence
RAL model generation by using ralgen tool by using XLS from designer. To create System level RAL model , use each IP RAL model and add offset of IP by providing offset in create_map function of uvm_reg_block.
Adaptor converts reg class to bus specific transaction. It has 2 inbuilt methods reg2bus and bus2reg. This adaptor connected to sequencer of register bus by set_sequencer method. And set_auto_predict to 1’b1.
After above setup , frontdoor access method of register class like write/read/update can be used.
This diagram shows the points explained above.