I2S Audio Overview

Three Signals : sck (clock) , sd (data) , ws (Word select) WS : Signal used to select Left or right audio Channel I2S supports only 2 channel.  can be TDM used to support 4,6,8 channel using I2S interface. TDM for Multichannel Same I2S interface for more than 2 channel. Each channel samples will be…

Packages in System Verilog

Here are some of points for packages in SV By default , if no package defined , variable will be in $unit package. It is good idea to have package which helps in code management and also for separate compilation flow. Generally Package should not have any dependency on other package or hierarchical path ,…

AXI4 Basics

AXI4 memory mapped transfer :  5 channels , AW , AR , W , B , R . valid and ready flow to trnafer request and data. valid should not depend on ready. AXI ID is for response reordering. So that slave can reponse to multipe requests in any order. How address is decided : …

Response from driver to sequencer

Driver and sequencer are connected by TLM push/pull port in UVM. If driver is getting response from interface and needs to be driven to sequence then same port can be used to send response back to sequence. For that response can be sent by using  seq_item_export.put(rsp)  in driver and sequence will use get_response(rsp) . By…

Code coverage 

Code coverage is used to know that how much code simulation able to cover. It is generated from simulation tool with extra arguments given. Here some of commands listed to generated code coverage by using different simulators. Add following with compile command  VCS       :  -cm line+cond+fsm+tgl+branch+assert -cm_dir $(PHY_SIM_LOG).vdb Questa :  +cover=bcesxf -coveropt…

Integration Of UVM VIP

When you have legacy environment in pure system verilog and wants to add new VIP in UVM to that test bench then following points will help. Passing interface to VIP agent from test bench top module using uvm_comfig_db set Take configuration object of VIP in system level test and pass to VIP agent using uvm_comfig_db…

Practical use of UVM RAL Model

UVM RAL model is Register Abstraction Layer which simplifies register verification of ASIC. It is actually mirror image class of register module in RTL in verification environment.  It is created by using uvm_reg_field , uvm_reg, uvm_reg_block . Simulation tools available which converts IP_XACT format register description to RAL model (e.g. ralgen) . Once register model…

Multithreading and Automatic variable

Below code will explains automatic vriable and multthreading. For below code , for case-1 and case-2 output is different , module my_module; int a=0; initial begin for(int i=0;i<5;i++) begin fork // Check differance here , between 2 statements // ##case 1 (declaration and assignment). automatic int j= i; // and automatic int j;  // ##case 2 declare j=i;…

Differance of FPGA and ASIC verification

 FPGA and ASIC functional verification differ majorly due to one part. It is due to its configuartion. ASIC configuration is done using register programming after reset and FPGA configuration is done using parameters. parameters needs to be passed at elaboration time. So cofiguration can not be done at run time for FPGA.So , ASIC like…

Pullup , Pulldown in verilog

For bidirectional bus mostly pullup/weak state is used on interface by default. It can be assigned by following way. 1 . pullup(io_dq) 2.  assign (weak1,weak0) io_dq = (direction) ? io : 1’bz; Below table shows different values for each strength . Strength Value Value displayed by display tasks supply 7 Su strong 6 St pull…