disable fork in SystemVerilog

If a process is started by fork .. join_any then it can be disabled by using disable fork or it can be disabled by using disable LABEL . There are some difference in using both these ways of disabling processes. Difference 1 : Here is example : fork  : process begin wait_for_clk(10) end begin wait_for_clk(40) end join_any  disable…

define usage in verilog and Macro

`define is very useful in verilog and here are some examples for that which will be useful to debug and develop smart macros. Simple usage of define is with ifdef and ifndef as shown . pass with compilation as  +define+XYZ `ifdef XYZ <code>  `endif   Define with some value associated with it. +define+ABC=2  Defines used…

Handling write and read file verilog

Functions used for writing and reading from file in verilog. fopen fclose fscanf  – read from file as per format fwrite – write to file as per format fdisplay -write to file Above Function are similar to C programming file handling. Difference of fwrite and fdisplay is that fwrite does not insert newline after each…

Write and Read all UVM Registers

UVM provides in built sequences to test registers like hw_reset and bit_bash . But , it is necessary to have sequence which write to all registers first and then read back.  Which will help to identify address aliasing issue. I have created uvm reg sequence which does this job. This sequence should be used same…

Experiments with uvm_event

Here , sharing some experiment with uvm_event. UVM 1.2 provides uvm_event as parameterized class. So I tried passing integer values by uvm_event , but it is not working with IUS. compilation error is coming from uvm library. ===================================== virtual function void trigger (T data=null); | ncelab: *E,TYCMPAT (/playground_lib/uvm-1.2/src/base/uvm_event.svh,300|42): assignment operator type check failed (expecting datatype…

I2S Audio Overview

Three Signals : sck (clock) , sd (data) , ws (Word select) WS : Signal used to select Left or right audio Channel I2S supports only 2 channel.  can be TDM used to support 4,6,8 channel using I2S interface. TDM for Multichannel Same I2S interface for more than 2 channel. Each channel samples will be…

Packages in System Verilog

Here are some of points for packages in SV By default , if no package defined , variable will be in $unit package. It is good idea to have package which helps in code management and also for separate compilation flow. Generally Package should not have any dependency on other package or hierarchical path ,…

AXI4 Basics

AXI4 memory mapped transfer :  5 channels , AW , AR , W , B , R . valid and ready flow to trnafer request and data. valid should not depend on ready. AXI ID is for response reordering. So that slave can reponse to multipe requests in any order. How address is decided : …

Response from driver to sequencer

Driver and sequencer are connected by TLM push/pull port in UVM. If driver is getting response from interface and needs to be driven to sequence then same port can be used to send response back to sequence. For that response can be sent by using  seq_item_export.put(rsp)  in driver and sequence will use get_response(rsp) . By…

Code coverage 

Code coverage is used to know that how much code simulation able to cover. It is generated from simulation tool with extra arguments given. Here some of commands listed to generated code coverage by using different simulators. Add following with compile command VCS       :  -cm line+cond+fsm+tgl+branch+assert -cm_dir $(PHY_SIM_LOG).vdb Questa :  +cover=bcesxf -coveropt…

Integration Of UVM VIP

When you have legacy environment in pure system verilog and wants to add new VIP in UVM to that test bench then following points will help. Passing interface to VIP agent from test bench top module using uvm_comfig_db set Take configuration object of VIP in system level test and pass to VIP agent using uvm_comfig_db…

Practical use of UVM RAL Model

UVM RAL model is Register Abstraction Layer which simplifies register verification of ASIC. It is actually mirror image class of register module in RTL in verification environment.  It is created by using uvm_reg_field , uvm_reg, uvm_reg_block . Simulation tools available which converts IP_XACT format register description to RAL model (e.g. ralgen) . Once register model…